1. Field of the Invention
The present invention relates non-volatile memory devices and, more particularly, to NAND-type flash memory devices including selection transistors with anti-punchthrough impurity regions and methods of fabricating the same.
2. Description of the Related Art
NAND-type flash memory devices typically exhibit a slower operating speed than NOR-type flash memory devices. However, NAND-type flash memory devices may have the advantage of integration density as compared to NOR-type flash memory devices. Therefore, NAND-type flash memory devices are widely used for storing image data of digital cameras or micro-codes of cellular phones, for example.
As NAND-type flash memory devices become more highly integrated, the short channel effect of cell transistors and selection transistors has been more serious. To suppress the short channel effect of the cell transistors and the selection transistors, a method of increasing channel concentration has been widely used. However, when the channel concentration of the cell transistors and the selection transistors is increased, some problems may occur. For example, channel capacitance and source/drain junction capacitance of the cell transistors may increase to degrade the self-boosting effect of a non-selected string in a programming mode. As a result, the cell transistors of the non-selected string may be programmed. Also, when the channel concentration of the selection transistors increases, the channel hot carrier effect of the selection transistors (particularly ground selection transistors) in the non-selected string may occur in a program mode. In this case, cell transistors adjacent to the selection transistors can be programmed. Therefore, there may limitations in suppressing the short channel effect of the selection transistors and cell transistors using a method of increasing the channel concentration.
FIG. 1 is a cross-sectional view illustrating a string of a NAND-type flash memory device disclosed in U.S. Pat. No. 5,677,556, and FIG. 2 is a cross-sectional view illustrating a non-selected string in a program mode of a conventional NAND-type flash memory device including the string shown in FIG. 1 and a bias condition applied to the non-selected string.
Referring to FIG. 1, a p-type well 11 is provided in an n-type semiconductor substrate 10, and an isolation layer (not shown) is formed in a predetermined region of the p-type well 11 to provide an active region. A string selection line 181 and a ground selection line 182 are disposed to cross over the active region, and first to eighth word lines 171 to 178 are disposed to cross over an active region between the string selection line 181 and the ground selection line 182. First to eighth floating gates 151 to 158 are interposed between the word lines 171 to 178 and the active region, respectively. The word lines 171 to 178 are insulated from the floating gates 151 to 158 by an inter-gate insulating layer 16, and the floating gates 151 to 158 are insulated from the active region (i.e., the p-type well 11) by a tunnel oxide layer 14. Further, the selection lines 181 and 182 are insulated from the p-type well 11 by the inter-gate insulating layer 16.
A bit line impurity region 131 is provided in the p-type well 11 that is adjacent to the string selection line 181 and opposite to the first floating gate 151, and a common source impurity region 132 is provided in the p-type well 11 that is adjacent to the ground selection line 182 and opposite to the eighth floating gate 158. The selection lines 181 and 182, the word lines 171 to 178, and the impurity regions 131 and 132 are covered with an insulating layer 19, and a conductive inversion gate 20 is provided on the insulating layer 19. The conductive inversion gate 20 extends into gap regions between the selection lines 181 and 182 and the word lines 171 to 178 to be adjacent to the p-type well 11. The conductive inversion gate 20 and the insulating layer 19 are covered with an interlayer insulating layer 21, and a bit line 22 is provided on the interlayer insulating layer 21. The bit line 22 passes through the interlayer insulating layer 21 and the insulating layer 19 and is electrically connected to the bit line impurity region 131.
In a program mode of a conventional NAND-type flash memory device, a non-selected string may be under the bias condition illustrated in FIG. 2.
Referring to FIG. 2, a program voltage may be applied to any one of the first to eighth word lines 171 to 178. For example, a program voltage of 20V may be applied to the second word line 172. In this case, a pass voltage of 10V may be applied to the first word line 171 and the third to eighth word lines 173 to 178, and 10V and 0V may be applied to the string selection line 181 and the ground selection voltage 182, respectively. Also, the common source impurity region 132 and the p-type well 11 are grounded to have a voltage of 0V, and a voltage of 10V may be applied to the bit line 22. Therefore, a ground selection transistor having the ground selection line 182, which functions as a gate electrode, is turned off, and channel inversion layers CH may be formed in channel regions below the word lines 171 to 178.
Furthermore, a high voltage of 20V may be applied to the inversion gate 20. As a result, source/drain inversion layers SD may be formed in the p-type well 11 between the channel inversion layers CH. The channel inversion layers CH and the source/drain inversion layers SD constitute an inversion layer INV that is electrically isolated from the common source impurity region 132. Accordingly, the inversion layer INV is self-boosted by coupling capacitance between the word lines 171 to 178, thereby having a voltage between a potential of the p-type well 11 and 10V.
To reduce the likelihood of all cell transistors of the non-selected string from being programmed, a boosted voltage of the inversion layer INV has to be high enough. A junction capacitance between the inversion layer INV and the p-type well 11 may be reduced to increase the boosted voltage of the inversion layer INV. In other words, the impurity concentration of the p-type well 11 may be lowered to increase the boosted voltage of the inversion layer INV. However, when the impurity concentration of the p-type well 11 is lowered, a leakage current IL may flow due to a punchthrough phenomenon between the inversion layer INV and the impurity regions 131 and 132. Particularly, the leakage current IL may easily flow between the inversion layer INV and the common source impurity regions 132.
When the leakage current IL flows between the inversion layer INV and the common source impurity regions 131 and 132 due to a punchthrough phenomenon, the boosted voltage of the inversion layer INV is lowered and the cell transistors of the non-selected string may be programmed. Furthermore, the inversion gate 20 may be interposed between the word lines 171 to 178 and the selection lines 181 and 182. Thus, there may be a limitation in reducing or minimizing space between the word lines 171 to 178 and the selection lines 181 and 182. Consequently, it may be difficult to improve the integration density of a NAND-type flash memory device due to the presence of the inversion gate 20.